In recent years, the mainland China market demand for semiconductor equipment is growing rapidly. Against this background, there is also an increasingly broad market for the high-precision test equipment that must be used for chip wafer testing. Because each functional component has its own testing needs, design engineers must develop test plans early in the design. In this article,wafer test we organize and share the chip test equipment and methods to you.

What equipment is needed for chip testing

Chip testing is mainly used for: chip testing machine, probe table, sorting machine and other testing equipment.

Chip tester

The tester is a specialized equipment for testing the function and performance of the chip. When testing, the tester applies input signals to the chip to be tested, and the output signals are compared with the expected value to determine the validity of the electrical performance of the chip and the function of the product. In the CP and FT testing session, the tester will transmit the results to the probe station and sorter respectively. When the Probe Station receives the test results,wafer level testing it performs an inkjet operation to mark defective chips on the wafer; when the Sorter receives the results from the Tester, it selects and sorts the chips.

Probe table

Probe table for wafer processing technology, packaging and processing technology design before the CP test a link, responsible for wafer delivery and product positioning, so that the wafer on the grain can be sequentially with the probe for contact and one by one to analyze the test. The work management flow of the probe table is as follows: move the wafer to the wafer camera through the carrier table, determine the wafer position through the wafer camera as well as shooting the wafer image, move the probes to different probe cards for the camera, determine the position of the probe head to be used, move the wafer to the probe card, and then realize the pairing of needles through the carrier table by constantly moving in the vertical development direction.

Sorting Machine

Sorting device is applied to the FT test link after chip packaging. It is a back-channel test equipment that provides chip screening and sorting functions. The sorter is responsible for transferring the input chips to the test module according to the system design. In this step, the classifier selects and categorizes the circuits based on the test results.

There are several commonly used methods for chip performance testing

There are six common methods for chip function test: board level test, wafer CP test, post-package Ft test, system level SLT test, reliability test, etc. The most common methods are board level test, wafer CP test, post-package Ft test, system level SLT test, and reliability test.

Board-level testing: mainly for functional testing, the use of PCB boards and chips to build a "simulation" of the chip's working environment, leading to all the interfaces of the chip to test the chip's function, failure analysis or to see whether the chip can work properly in a variety of harsh environments. The equipment to be applied is mainly instrumentation, and EVB evaluation boards need to be made.

System-level SLT test: often used in social function analysis test, performance and test and reliability test, often can be used as a supplement to the enterprise finished product FT test and exists, as the name suggests, is in such an information system development environment for management testing, that is, the chip is put into the environment where it is normal to teach the work of the function of the function to detect the good and bad, the disadvantage is that it can only be covered by a part of the function, the coverage is low so we generally is the chip can work normally under various harsh environments. The disadvantage is that it can only cover part of the functions, and the coverage rate is low, so we are generally the supplementary legal means of FT.

Reliability testing: mainly for the chip to impose a variety of harsh environments, such as electrostatic discharge static electricity, is a simulation of the human body or industrial body to the chip to increase the large voltage test moment.

FT test of packaged product: Commonly used in function test, performance test and reliability test, to check whether the function of the chip is normal, whether there are defects in the packaging process, in the reliability test to help detect whether the chip can still work after "fire, snow, lightning".

Wafer CP Test: Commonly used for functional and performance testing to understand whether the chip functions normally and to screen out faulty chips in the wafer.

Multi-strategy Simultaneous Testing: According to our testing needs, we use multiple testing methods to conduct combined testing at the same time.

In the semiconductor design, manufacturing, packaging in the various teaching aspects of the students to carry out a repeated multiple testing, testing to ensure that the quality of corporate product services, so as to develop a device to meet the requirements of the development of social systems. Defects and associated fault management are costly, ranging from tens of dollars at the IC level, to hundreds of dollars at the module level, to thousands of dollars at the application-side level. As a result, inspection network devices have their own irreplaceable and economically important position from design method validation to the entire semiconductor manufacturing production process.